Drift Region Effects of Power MOSFETs

Improvement in process technology helps choose different materials in addition to shrinking devices. The power MOS device and laterally diffused metal oxide semiconductor device (LDMOS) designed in this paper was simulated by semiconductor process simulation software, and manufactured by using process machine parameters of National Nano Device Laboratories (NDL). In the paper, it also explores that the device drift region length variation affected on breakdown voltage of the device. In device design, the 3:4 aspect ratio shallow trench isolation device architecture was used for simulation to achieve a device with 10.4V (BV) breakdown voltage. Based on these parameter obtained, the power MOS device made can actually withstand high voltage with measured breakdown voltage at 8.5V. However, regard to laterally diffuse metal oxide semiconductor device, we will explore the epitaxial layer thickness effect on the device´s ability to withstand voltage. When epitaxial layer thickness is increased, the ability to withstand voltage been enhanced up to 50%. By contrast, the ability to withstand voltage been reduced up to 44% when epitaxial layer thickness is decreased.