Low-leakage and low-power implementation of high-speed 65nm logic gates

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.