A 1-V, 81-dB, 780-KS/s, sigma-delta modulator in 0.13-μm digital CMOS technology

A low-voltage discrete time forth-order Sigma-Delta modulator using input feed-forward is implemented. With careful signal scaling, signal swings inside the loop filter are suppressed to less than 50% of the reference voltage, which is highly desirable for low-voltage designs. The proposed single-loop single-bit input feed-forward topology is a simple and robust solution for low-voltage low-power Sigma-Delta ADC design in deep sub-micron CMOS technologies. Implemented with a 0.13-mum pure digital CMOS technology, the Sigma-Delta modulator achieves 780-KS/s conversion speed and 81-dB peak SNDR with 35-mW power dissipation under 1.0-V power supply voltage.