Title :
Modeling of dynamic threshold voltage in high K gate stack and the application in FinFET reliability
Author :
Ma, Chenyue ; Li, Bo ; Zhang, Lining ; He, Jin ; Zhang, Xing ; Lin, Xinnan
Author_Institution :
Shenzhen Grad. Sch., Peking Univ., Shenzhen
Abstract :
A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of Id is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.
Keywords :
MOSFET; SPICE; high-k dielectric thin films; semiconductor device models; semiconductor device reliability; FinFET reliability; HSPICE; MOSFETs; drain circuit degradation; dynamic threshold voltage modeling; fast transient charging effect; high K gate stack; reverser delay time; slow transient charging effect; Circuit simulation; Degradation; Electron traps; FinFETs; Helium; High K dielectric materials; High-K gate dielectrics; MOSFETs; Stress; Threshold voltage;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-2539-6
Electronic_ISBN :
978-1-4244-2540-2
DOI :
10.1109/EDSSC.2008.4760661
