A high reliability CMOS implantable interface for wireless neural recording microsystem

Author

Hongge Li ; Zhang, Youguang

Author_Institution

Sch. of Electron. Inf. Eng., Beijing Univ. of Aeronaut. & Astronaut., Beijing

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A novel wireless implantable microsystem using a high-reliability digital technology is proposed for recording the hybrid neural signal. In order to enhance the neural recording intactness, we employ a kind of high-reliability design architecture, which includes a self-check circuit and a transmitter channel error check circuit. The proposed high-reliability structure can identify possible faults in any implantable interface. A dynamical pattern double channel circuit is designed for the signal synchronous transfer in this interface. A low-power self-check circuit is designed too. The high-reliability and low-power implantable interface using a full-CMOS technology has been designed and verified. A prototype has been implemented, whose correct operation has been verified by mean of post-layout simulations and experimental measurements.

Keywords

CMOS integrated circuits; built-in self test; integrated circuit reliability; low-power electronics; micromechanical devices; dynamical pattern double channel circuit; high reliability CMOS implantable interface; self check circuit; signal synchronous transfer; transmitter channel error check circuit; wireless implantable microsystem; wireless neural recording microsystem; CMOS technology; Circuit faults; Circuit simulation; Digital recording; Fault diagnosis; Neurotransmitters; Signal design; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-2539-6

Electronic_ISBN

978-1-4244-2540-2

Type

conf

DOI

10.1109/EDSSC.2008.4760664

Filename

4760664