A modified high-performance structure of low-voltage CMOS Op-amp

A modified high-performance structure of low-voltage CMOS folded-cascode op-amp for switched-capacitor (SC) applications, with a 50 MHZ clock-frequency and a single 2V supply voltage, is presented. The proposed two-stage OTA is a A/AB class that combines a novel rail-to-rail folded-cascode as the first-stage with active current mirrors as the second stage. Due to the AB class operation in the second stage, slew limiting only occurs in the first stage, So, it cause lower power dissipation for SC circuits. Also, it employs the cascode compensation scheme for fast settling. Using the proposed methodology, the optimum values for the op-amp device sizes of all stages are determined in order to optimize all of the characteristics. Trade-offs among such factors as bias-current, speed, noise and power-dissipation are made evident. This op-amp is designed in 0.18 um and 0.35 um CMOS (level 49) twin-well TSMC process, and is simulated with Hspice. Finally, this structure is checked for a typical switched-capacitor integrator, and with all process corners from -50degc to +100degc.