DocumentCode :
2466708
Title :
A real-time encoding/decoding system (REDS) for HDTV editing
Author :
Jeon, J.H. ; Park, Y.S. ; Lee, C.S. ; Kang, J. ; Park, J.H. ; Yoon, D.S. ; Park, H.W.
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fYear :
1998
fDate :
7-9 Dec 1998
Firstpage :
215
Lastpage :
220
Abstract :
A programmable and scalable parallel architecture is proposed for the real-time encoding/decoding of HDTV images and for nonlinear editing of the compressed video data. It only uses the intra-mode compression/decompression so that nonlinear editing can be performed easily and high-quality images can be recovered. Spatially partitioned image data are concurrently processed by multiple parallel processing units (PUs). Each PU consists of a programmable parallel digital signal processor, called multimedia video processor (MVP; TMS320C80), and reconfigurable field programmable logic devices (FPLDs). The performance of the REDS is described in terms of the required MVP cycles for transform coding and the FPLDs throughput for entropy coding. Robust rate distortion-optimized quantization matrices for HDTV images are presented
Keywords :
decoding; digital signal processing chips; entropy codes; high definition television; multimedia systems; parallel architectures; programmable logic devices; real-time systems; signal flow graphs; transform coding; video coding; FPLD throughput; HDTV editing; HDTV images; REDS; TMS320C80; compressed video data; entropy coding; high-quality images; intra-mode compression/decompression; multimedia video processor; multiple parallel processing units; nonlinear editing; programmable parallel architecture; programmable parallel digital signal processor; rate distortion-optimized quantization matrices; real-time encoding/decoding system; reconfigurable field programmable logic devices; scalable parallel architecture; spatially partitioned image data; transform coding; Decoding; Digital signal processors; Encoding; HDTV; Image coding; Parallel architectures; Parallel processing; Programmable logic devices; Real time systems; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia Signal Processing, 1998 IEEE Second Workshop on
Conference_Location :
Redondo Beach, CA
Print_ISBN :
0-7803-4919-9
Type :
conf
DOI :
10.1109/MMSP.1998.738937
Filename :
738937
Link To Document :
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