Title :
Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology
Author :
Wang, Bo ; Chen, Dianyong ; Liao, Andrea ; Liang, Bangli ; Kwasniewski, Tadeusz
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON
Abstract :
In this paper, we discuss an optimized current-mode logic (CML) circuit design technique for high-speed backplane transmission. The inductorless CML circuits are extensively used in high-speed digital circuits. With a given CMOS technology, the CML circuits can be optimally biased for higher speed operation with the considerations of speed, swing, power, load capacitance and area. Typical high-speed CML buffer and latch for 10-Gb/s transmission are designed with the optimized biasing technique with lower power consumption, and compact area (buffer: 10.2 times 14.4 mum2, latch: 30.4 times 32.8 mum2).
Keywords :
CMOS logic circuits; buffer circuits; current-mode circuits; flip-flops; integrated circuit design; CMOS technology; bit rate 10 Gbit/s; buffer; current-mode logic circuit design; high-speed backplane transmission; high-speed digital circuits; latch; load capacitance; power consumption; Backplanes; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Design optimization; Digital circuits; Latches; Logic circuits; Logic design;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-2539-6
Electronic_ISBN :
978-1-4244-2540-2
DOI :
10.1109/EDSSC.2008.4760694
