ESD device simulation in a pre-Si phase

In this paper, a novel approach that performs device simulation in the pre-Si phase to evaluate the robustness of the ESD protection device is presented. Several key parameters, such as the spacing from gate to source contact, the spacing from gate to drain contact, the length of the gate and the width of the gate are researched using the simulator MEDICI. Tunneling phenomenon is also observed and expatiated in ESD protection device. An empirical equation is derived based on the simulation to calculate the failure threshold of the device. The prediction of ESD protection circuit performance in early design phase shortens the design cycle and reduces the cost.