Title :
Design of dual-gigabit transceiver for fibre channel FC-1 layer
Author :
Sun, Guicai ; Yu, Dunshan
Author_Institution :
Inst. of Microelectron., Peking Univ. of Beijing, Beijing
Abstract :
Fibre channel is a gigabit-speed network technology which dominates todaypsilas high-end storage network market. Its topology consists of several layers. This paper presents a transceiver design with FS-HSPI compliant interface used for Fibre Channel Transmission Protocol Layer.. or FC-1 layer. Optimized 8B/10B encoder/decoder architecture and parallel CRC checking algorithm are used in order to satisfy high-speed requirements and ensure reliability during transmission. By providing DDR/SDR interface, the transceiver can support both 1.0625 Gbit/s and 2.125 Gbit/s transmission rate. FIFO buffering and clock correction technique are used to accommodate the rate difference between recovered clock and receiver clock. Synthesis results using Synopsys Design Compiler in SMIC 0.18 um technology shows our design can reach the required baud rate.
Keywords :
clocks; decoding; encoding; optical communication equipment; optical fibre networks; protocols; transceivers; Synopsys design compiler; bit rate 1.0625 Gbit/s to 2.125 Gbit/s; buffering; checking algorithm; clock correction technique; dual-gigabit transceiver; encoder-decoder architecture; fibre channel transmission protocol layer; gigabit-speed network technology; high-end storage network market; transceiver design; Circuits; Clocks; Cyclic redundancy check; Decoding; Design optimization; Frequency; Network topology; Protocols; Sun; Transceivers;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-2539-6
Electronic_ISBN :
978-1-4244-2540-2
DOI :
10.1109/EDSSC.2008.4760719
