DocumentCode :
2467343
Title :
A two-stage simulated annealing methodology
Author :
Varanelli, James M. ; Cohoon, James P.
Author_Institution :
Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
fYear :
1995
fDate :
16-18 Mar 1995
Firstpage :
50
Lastpage :
53
Abstract :
We propose a two-stage simulated annealing method. While most previous work has focused on ad hoc constant starting temperatures for the low temperature annealing phase, this paper presents a more formal method for starting temperature determination in two-stage simulated annealing systems. We have successfully applied our method to three optimization problems using both classic and adaptive schedules. We also briefly discuss an alternative stop criterion that experimentally reduces the running time up to an additional ten percent in our problem suite
Keywords :
VLSI; circuit CAD; circuit optimisation; integrated circuit design; simulated annealing; CAD; VLSI; adaptive schedules; formal method; optimization problems; problem suite; running time; starting temperature determination; stop criterion; two-stage simulated annealing methodology; Computational modeling; Computer science; Computer simulation; Cooling; Costs; Measurement standards; Optimization methods; Simulated annealing; Temperature; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
ISSN :
1066-1395
Print_ISBN :
0-8186-7035-5
Type :
conf
DOI :
10.1109/GLSV.1995.516023
Filename :
516023
Link To Document :
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