DocumentCode
2467477
Title
A Hardware Implementation Method of Multi-Objective Genetic Algorithms
Author
Tachibana, Tatsuhiro ; Murata, Yoshihiro ; Shibata, Naoki ; Yasumoto, Keiichi ; Ito, Minoru
fYear
0
fDate
0-0 0
Firstpage
3153
Lastpage
3160
Abstract
Multi-objective genetic algorithms (MOGAs) are approximation techniques to solve multi-objective optimization problems. Since MOGAs search a wide variety of pareto optimal solutions at the same time, MOGAs require large computation power. In order to solve practical sizes of the multi objective optimization problems, it is desirable to design and develop a hardware implementation method for MOGAs with high search efficiency and calculation speed. In this paper, we propose a new method to easily implement MOGAs as high performance hardware circuits. In the proposed method, we adopt simple Minimal Generation Gap (MGG) model as the generation model, because it is easy to be pipelined. In order to preserve diversity of individuals, we need a special selection mechanism such as the niching method which takes large computation time to repeatedly compare superiority among all individuals in the population. In the proposed method, we developed a new selection mechanism which greatly reduces the number of comparisons among individuals, keeping diversity of individuals. Our method also includes a parallel execution architecture based on Island GA which is scalable to the number of concurrent pipelines and effective to keep diversity of individuals. We applied our method to multi-objective Knapsack Problem. As a result, we confirmed that our method has higher search efficiency than existing method.
Keywords
Pareto optimisation; approximation theory; genetic algorithms; knapsack problems; pipeline processing; approximation techniques; concurrent pipelines; hardware circuits; hardware implementation method; island GA; minimal generation gap; multiobjective genetic algorithms; multiobjective knapsack problem; niching method; pareto optimal solutions; special selection mechanism; Ant colony optimization; Circuits; Field programmable gate arrays; Genetic algorithms; Hardware; Indium tin oxide; Information processing; Information science; Pipelines; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolutionary Computation, 2006. CEC 2006. IEEE Congress on
Conference_Location
Vancouver, BC
Print_ISBN
0-7803-9487-9
Type
conf
DOI
10.1109/CEC.2006.1688708
Filename
1688708
Link To Document