Novel asymmetric MOSFET structures for low power applications

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short channel effects (DIBL and V_TH roll-off), off-state and gate leakage, parasitic capacitance and resistance severely limit the performance of these transistors. These, in addition to V_DD scaling limitation and high sub-threshold swing (>60 mv/dec) give rise to high I_OFF and make power dissipation an enormous challenge, especially for low power/low current applications. New device innovations are essential to achieve low I_OFF and high g_m with high R_OUT for digital and analog applications respectively. Towards this end, novel asymmetric Tunneling Source MOSFETs are proposed in this paper. The main feature of these devices is the concept of gate controlled carrier injection through tunneling at the source junction. The tunneling source MOSFETs can be fabricated using conventional CMOS processes. These novel devices have the potential for steep sub-threshold behavior, improved I_ON/I_OFF, high R_OUT and gain (g_m times R_OUT) at low bias currents. They also possess excellent immunity against short channel effects which improves scalability into sub-50 nm regime and makes them an attractive candidate for low power digital and analog operations.