Title :
Design and analysis of a low-power energy-recovery adder
Author :
Tzartzanis, Nestoras ; Athas, William C.
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
Abstract :
In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies
Keywords :
CMOS logic circuits; SPICE; VLSI; adders; circuit CAD; circuit analysis computing; delays; integrated circuit design; logic CAD; CMOS logic circuits; SPICE simulation; VLSI; delay time; energy dissipation; energy-recovery adder; frequency range; Adders; Capacitance; Circuits; Clocks; Drives; Energy dissipation; Latches; Logic; Power supplies; Voltage;
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
Print_ISBN :
0-8186-7035-5
DOI :
10.1109/GLSV.1995.516026
