Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes

In the past decade, we observed the trend of technological advancement towards the field of portable electronics. As electronic devices shrink in size, constraints emerge in the form of limited power supply and area for the implementation of information security mechanisms. In this work, our goal is to produce a complete AES block cipher for data encryption and perform optimization in terms of power and size. Unlike the common approach of optimizing the circuitry of the expensive AES S-Box, this work contributes by proposing a compact key expansion mechanism to reduce hardware requirement and deducing the optimal number of S-Boxes to be used in an AES block cipher to achieve the desired performance. In addition, we optimized the design using a series of methodologies which include: (1) implementing the optimized AES S-Box proposed by Wong et al. [2], (2) reducing the number of pipeline registers, and (3) applying input bus sharing. As a result, we achieved three optimized configurations which employ different number of S-Boxes in their architectures. Our best architecture in terms of size and power consumption has a total logic element count of 1818, a total power dissipation of 122.40mW, and a throughput of 198.77Mbps. The design is implemented on a Cyclone II EP2C20F484C7 field-programmable gate array (FPGA).