Abstract :
Summary form only given, as follows. The density and speed of sub-50nm CMOS technology enables the design of multi-functional SoCs for highly integrated, mobile, communication devices. At the same time, process variations, power issues and complexity of scope are challenging even the most advanced simulation capabilities. The growing design complexity is addressed by rapidly improving modeling of systematic manufacturing variations and design sensitivities. Physical design is becoming more structured to allow for process optimized design rules and efficient automation. While challenges remain in the scaling and optimization of analog and I/O functions, highly integrated, mobile communication devices are a major driving force for continued economies of scaling.
