A SoPC architecture for nearest-neighbor based learning and recognition

This paper proposes an efficient and flexible nearest-neighbor-based learning and recognition system on a programmable chip. The nearest neighbor search (NNS), which is a common computational problem in pattern recognition, is to find the minimal distance among all distances between an unknown sample and the complete set of the often high-dimensional reference database. In this paper, a reference optimization learning stage based on NNS is used to reduce the storage space of references and to speed-up the recognition. For efficiently solving the NNS computational problem, we present a specialized hardware implementation with p-component-parallel word-serial pipelined architecture based on the DSP blocks in Stratix FPGA device, used as NNS co-processor. For flexibility, the FPGA embedded processor, Altera´s Nios II processor, is used for reference optimization which is the higher level part in the learning stage. Due to the hardware and embedded software cooperation, high-speed learning and recognition based on NNS can be carried out on a programmable FPGA.