DocumentCode :
2468379
Title :
A reconfigurable design-for-debug infrastructure for SoCs
Author :
Abramovici, Miron ; Bradley, Paul ; Dwarakanath, Kumar ; Levin, Peter ; Memmi, Gerard ; Miller, Dave
Author_Institution :
DAFCA, Inc., Framingham, MA
fYear :
0
fDate :
0-0 0
Firstpage :
7
Lastpage :
12
Abstract :
In this paper we present a design-for-debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters
Keywords :
design for testability; integrated circuit design; integrated circuit testing; reconfigurable architectures; system-on-chip; JTAG port; assertion checkers; distributed reconfigurable fabric; event counters; functional debug; reconfigurable design-for-debug infrastructure; system-on-chip; transaction identifiers; Counting circuits; Design engineering; Design for disassembly; Fabrics; Hardware; Instruments; Observability; Permission; Silicon; Time to market; Design; Economics; Experimentation; Performance; Silicon debug; Verification; assertion-based debug; at-speed debug; what-if experiments;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
1-59593-381-6
Type :
conf
DOI :
10.1109/DAC.2006.238683
Filename :
1688751
Link To Document :
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