DocumentCode
2468471
Title
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
Author
Tanimoto, Tadaaki ; Yamaguchi, Seiji ; Nakata, Akio ; Higashino, Teruo
fYear
0
fDate
0-0 0
Firstpage
37
Lastpage
42
Abstract
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus based system while satisfying given end-to-end real-time constraints of the entire system such as throughput and latency constraints. In this paper, we define a bus scenario representing a set of possible execution sequences of tasks and bus transfers executed in a bus based system. Then we propose a method for deriving real time budgets of all the tasks running in parallel and pipelined fashion from the pair of a system configuration (such as bus topology) and a bus scenario. In deriving such real time budgets, we consider computational complexity of each task, the amount of bus transfers and bus arbitration policies (e.g. fixed priority or time divided round robin based arbitration). We show that the proposed method is effective for designing several bus based systems such as MPEG decoders
Keywords
integrated circuit design; logic design; parallel architectures; bus arbitration policies; bus scenarios; bus topology; bus transfers; module-level-pipelined bus based system; parallel architecture; pipelined architecture; real time budgeting method; Computational complexity; Delay; Information science; Processor scheduling; Real time systems; Scheduling algorithm; Software algorithms; System-on-a-chip; Throughput; Topology; Bus based systems; Cycle budgeting; Design; Multimedia processing; Performance; Pipelined processing; Real-time systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229173
Filename
1688756
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