DocumentCode
2468535
Title
Statistical analysis of SRAM cell stability
Author
Agarwal, Kanak ; Nassif, Sani
Author_Institution
IBM Res., Austin, TX
fYear
0
fDate
0-0 0
Firstpage
57
Lastpage
62
Abstract
The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extremes
Keywords
Monte Carlo methods; SRAM chips; circuit stability; integrated circuit modelling; integrated circuit noise; integrated circuit reliability; integrated circuit yield; DC noise; Monte-Carlo simulations; SRAM cell stability; cell failure; memory cell; statistical analysis; Design optimization; Error correction codes; Fluctuations; Inverters; Random access memory; Random variables; Semiconductor process modeling; Stability analysis; Statistical analysis; Threshold voltage; Design; Performance; Reliability; SRAM; modeling; noise margin; reliability; stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229176
Filename
1688760
Link To Document