DocumentCode
2468695
Title
CMOS circuit speed optimization based on switch level simulation
Author
Yuan, Jiren ; Svensson, Christer
Author_Institution
LSI Design Center, Linkoping Univ., Sweden
fYear
1988
fDate
7-9 June 1988
Firstpage
2109
Abstract
The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.<>
Keywords
CMOS integrated circuits; circuit analysis computing; integrated circuit technology; optimisation; CMOS circuit speed optimization; SLOP; delay-area curve; maximum width limitation; switch level simulation; transistor sizing; Adders; Capacitance; Circuit simulation; Clocks; Delay; Design optimization; SPICE; Semiconductor device modeling; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15358
Filename
15358
Link To Document