Symbolic execution of data paths

Author

Monahan, Chuck ; Brewer, Forrest

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

1995

fDate

16-18 Mar 1995

Firstpage

80

Lastpage

85

Abstract

We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model´s base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor

Keywords

Boolean functions; combinational circuits; combinational switching; constraint handling; data flow analysis; data flow graphs; digital signal processing chips; hazards and race conditions; logic design; processor scheduling; Boolean functions; DSP microprocessor; bus hazards; combinational logic; connection constraints; control encoding limitations; data-path model; dataflow graphs; memory elements; operand constraints; path constraints; path-constrained model; register constraints; scheduling; switching logic; symbolic execution; Boolean functions; Digital signal processing; Hazards; Logic; Microprocessors; Network synthesis; Power system modeling; Processor scheduling; Registers; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516029

Filename

516029