Title :
SystemC transaction level models and RTL verification
Author_Institution :
Cadence Design Syst., Inc., San Jose, CA
Abstract :
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models
Keywords :
hardware description languages; hardware-software codesign; integrated circuit design; system-on-chip; SystemC; register transfer level verification; system-on-chip; transaction level models; Circuit simulation; Embedded software; Hardware design languages; Integrated circuit modeling; Permission; Software standards; Software systems; Standardization; System-on-a-chip; Wires; Hardware/Software Co-Design; Hardware/Software Co-Verification; Languages; RTL Verification; Standardization; SystemC; TLM; Transaction Level Model; Verification;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229170
