DocumentCode
2468939
Title
Refined statistical static timing analysis through learning spatial delay correlations
Author
Lee, Benjamin N. ; Wang, Li -C ; Abadir, Magdy S.
Author_Institution
Dept. of ECE, California Univ., Santa Barbara, CA
fYear
0
fDate
0-0 0
Firstpage
149
Lastpage
154
Abstract
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits
Keywords
Bayes methods; integrated circuit modelling; integrated circuit testing; network analysis; statistical analysis; Bayesian approach; path delay testing; spatial delay correlations; statistical static timing analysis; statistical timing models; Bayesian methods; Circuits; Delay effects; Environmental economics; Impedance; Performance analysis; Silicon; Spatial resolution; Testing; Timing; Algorithms; Bayesian learning; Design; Performance; Statistical timing; delay correlations;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229198
Filename
1688779
Link To Document