Synthesis of SEU-tolerant ASICs using concurrent error correction

Author

Hollander, Harry ; Carlson, Bradley S. ; Bennett, Toby D.

Author_Institution

Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

fYear

1995

fDate

16-18 Mar 1995

Firstpage

90

Lastpage

93

Abstract

We present a new design technique for the concurrent error correction of single event upsets in the memory elements of ASICs. The technique uses a single error correction/double error detection (SEC/DED) Hamming code to encode the content of the memory elements. The area and delay overhead and error-correction capability are optimized by partitioning the set of memory elements. Design experiments show our technique is feasible, and it can be applied to any ASIC technology

Keywords

Hamming codes; application specific integrated circuits; circuit layout CAD; error correction codes; logic CAD; logic partitioning; radiation hardening (electronics); sequential circuits; SEU-tolerant ASIC synthesis; area overhead; concurrent error correction; delay overhead; design experiments; fault tolerant design; memory element set partitioning; memory elements; sequential circuit; single error correction/double error detection Hamming code; single event upsets; Application specific integrated circuits; Circuit synthesis; Decoding; Delay; Error correction; Error correction codes; Flip-flops; Logic circuits; Single event upset; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516031

Filename

516031