Title :
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Author :
Li, Peng ; Shi, Weiping
Author_Institution :
Dept. of ECE, Texas A&M Univ., College Station, TX
Abstract :
Model order reduction has been a driving force for reducing analysis complexity of VLSI systems containing large linear networks. However, most existing reduction techniques are only applicable to networks with a small number of ports, failing to fulfill an even stronger need of reducing massively interconnected subsystems such as power grids and wide buses. In this paper, a port packing scheme is presented wherein the correlation between circuit ports is explored in a frequency-dependent manner. In the proposed McPack (multiport circuit packing) algorithm, port packing is combined with a practical realization of the recently developed tangential interpolation scheme for model reduction. McPack performs feasible moment matching for networks with many ports in the sense of tangential interpolation. With guaranteed passivity, extensibility to multi-point expansion as well as comparable complexity, McPack systematically introduces frequency-domain port packing into the existing projection-based model order reduction framework. For several large networks with high port count, the presented algorithm is shown to be significantly more accurate than the standard block-moment matching algorithm as well as other recently developed alternative
Keywords :
VLSI; frequency-domain analysis; interpolation; linear network analysis; multiport networks; reduced order systems; McPack algorithm; block-moment matching algorithm; circuit ports; frequency-dependent port packing; frequency-domain port packing; linear networks; model order reduction; moment matching; multiport circuit packing algorithm; tangential interpolation; Circuit simulation; Frequency; Integrated circuit interconnections; Interpolation; Power grids; Power system modeling; RLC circuits; Reduced order systems; Transfer functions; Very large scale integration; Algorithms; Model order reduction; Performance; Verification; multi-port networks;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229222