DocumentCode :
2469483
Title :
A compact parasitic-insensitive dual-frequency ΔΣ modulated CMOS capacitive architecture
Author :
Singh, Ritu Raj ; Abdelhalim, Karim ; Genov, Roman
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
fYear :
2010
fDate :
3-5 Nov. 2010
Firstpage :
242
Lastpage :
245
Abstract :
We present a simple, high-sensitivity, array-based capacitive sensing architecture for biological applications. Conventional charge based capacitance measurement (CBCM) techniques sense grounded coupling capacitances along with unwanted parasitics. These parasitics can be orders of magnitude higher than the coupling capacitances, thus severely reducing the usable sensor dynamic range. The presented architecture utilizes an accurate charge integration technique to attenuate the effect of unwanted parasitics. Unlike CBCM, the architecture can also perform capacitance-voltage profiling of nonlinear biological capacitances at very low voltages. The architecture includes a first order ΔΣ modulator with dual input frequency to increase the sensor dynamic range. We verify the circuit implemented in a 0.35μm CMOS technology by simulating for different values of parasitic capacitances, process corners and varying test voltages across capacitors.
Keywords :
CMOS integrated circuits; capacitance measurement; sigma-delta modulation; CMOS capacitive architecture; CMOS technology; charge based capacitance measurement techniques; grounded coupling capacitances; parasitic capacitances; parasitic-insensitive dual-frequency sigma delta; process corners; size 0.35 mum; test voltages; Capacitance measurement; Capacitors; Computer architecture; Dynamic range; Modulation; Parasitic capacitance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Biomedical Circuits and Systems Conference (BioCAS), 2010 IEEE
Conference_Location :
Paphos
Print_ISBN :
978-1-4244-7269-7
Electronic_ISBN :
978-1-4244-7268-0
Type :
conf
DOI :
10.1109/BIOCAS.2010.5709616
Filename :
5709616
Link To Document :
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