DocumentCode
2469530
Title
Hierarchical power distribution and power management scheme for a single chip mobile processor
Author
Hattori, Toshihiro ; Irita, Takahiro ; Ito, Masayuki ; Yamamoto, Eiji ; Kato, Hisashi ; Sado, Go ; Yamada, Tetsuhiro ; Nishiyama, Kunihiko ; Yagi, Hideki ; Koike, Takao ; Tsuchihashi, Y. ; Higashida, Motoki ; Asano, Hiroyuki ; Hayashibara, Izumi ; Tatezaw
Author_Institution
Renesas Technol. Corp., Tokyo
fYear
0
fDate
0-0 0
Firstpage
292
Lastpage
295
Abstract
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU\´s that is baseband processor, application processor, and multimedia processor. In the "waiting for calling" mode of the mobile handsets, application processor and multimedia processor part can be power-off. This chip can power off these power domains although the some of baseband parts are actively operating. Many new techniques for multiple power domains in the chip are described
Keywords
integrated circuit design; leakage currents; microprocessor chips; mobile handsets; mobile radio; application processor; baseband processor; hierarchical power distribution; leakage current; mobile handsets; multimedia processor; partial active mode; power management scheme; single chip mobile processor; Baseband; Cellular phones; Clocks; Computer architecture; Energy management; Indium tin oxide; Power distribution; Repeaters; Ultra large scale integration; Very large scale integration; Design; VLSI; mobile processor; partial power off; power domain;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229251
Filename
1688808
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