Title :
A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS
Author :
Ananthan, Hari ; Roy, Kaushik
Author_Institution :
Dept. of ECE, Purdue Univ., West Lafayette, IN
Abstract :
Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal technology and circuit design choices. This paper presents a fully physical model for double-gate leakage distribution due to gate length (L) and body thickness (tsi) variations, both for single devices and stacks. The model is derived directly from the solution of Poisson´s and Schrodinger´s equations, and thus captures the effect of unique double-gate phenomena such as volume inversion and quantum confinement. It is scalable to L = 13nm and tsi = 3nm, with less than 2% error for 3sigma variation as large as 20% of nominal process parameters
Keywords :
CMOS integrated circuits; MOSFET; Poisson equation; Schrodinger equation; integrated circuit design; leakage currents; 32 nm; FinFET; Poisson equations; SOI technologies; Schrodinger equations; body thickness variations; circuit design; gate length; leakage distribution; nanoscale double-gate CMOS; nominal process parameters; optimal technology; process variations; quantum confinement; volume inversion; CMOS process; CMOS technology; Circuit synthesis; FinFETs; Integrated circuit technology; Integrated circuit yield; Nanoscale devices; Permission; Potential well; Semiconductor device modeling; Design; Double-gate; FinFET; Leakage Distribution; Multiple-gate; Process Variations; Theory; Tri-gate;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229223
