A parallelized way to provide data encryption and integrity checking on a processor-memory bus

Author

Elbaz, Reouven ; Torres, Lionel ; Sassatelli, Gilles ; Guillemin, Pierre ; Bardouillet, Michel ; Martinez, Albert

Author_Institution

LIRMM UMR, Montpellier Univ.

fYear

0

fDate

0-0 0

Firstpage

506

Lastpage

509

Abstract

This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee confidentiality and integrity of data exchanged between a SoC (system on chip) and its external memory. The PE-ICE approach is based on an existing block-encryption algorithm to which the integrity checking capability is added. Simulation results show that the performance overhead of PE-ICE remains low (below 4%) compared to block-encryption-only systems (which provide data confidentiality only)

Keywords

cryptography; electronic data interchange; system buses; system-on-chip; PE-ICE; SoC; block-encryption algorithm; block-encryption-only systems; data confidentiality; data encryption; data exchanged; parallelized encryption and integrity checking engine; processor-memory bus; system on chip; Algorithm design and analysis; Computational modeling; Cryptography; Data security; Engines; Information security; Microcomputers; Portable computers; Splicing; System-on-a-chip; Algorithms; Architectures; Bus Encryption; Data Confidentiality and Integrity; Design; Performance; Security; Verification;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2006 43rd ACM/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

1-59593-381-6

Type

conf

DOI

10.1109/DAC.2006.229264

Filename

1688850