A formal approach towards electrical verification of synchronous MOS circuits

Author

Bolsens, Ivo ; De Rammelaere, W. ; Van Overloop, C. ; Claesen, L. ; De Man, H.

Author_Institution

IMEC Lab., Leuven, Belgium

fYear

1988

fDate

7-9 June 1988

Firstpage

2113

Abstract

The authors present a formal view on the analysis of the electrical behavior of synchronous MOS circuits. Rule-based techniques are used to derive the intended behavior of the transistor schematics by applying rules of common sense, to increase the efficiency of the verification procedures by topological rules that recognize known circuit configurations and to locally approve specific subcircuits by applying provable correct rules. The combination of rule-based verification methods and fundamental algorithms, founded on a formal theory, makes it possible to generate the relevant error messages. The overall approach is a mixture of expert-system techniques and procedural programming.<>

Keywords

MOS integrated circuits; circuit analysis computing; circuit layout CAD; network topology; circuit configurations; electrical verification; error messages; expert-system techniques; formal theory; procedural programming; rule-based verification methods; synchronous MOS circuits; topological rules; transistor schematics; Capacitance; Circuit optimization; Circuit simulation; Circuit synthesis; Clocks; Digital circuits; Integrated circuit reliability; Physics; Software tools; Terminology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15359

Filename

15359