Performance driven standard-cell placement using the genetic algorithm

Author

Youssef, Habib ; Sait, Sadiq M. ; Nassar, Khaled ; Benten, Muhammad S T

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1995

fDate

16-18 Mar 1995

Firstpage

124

Lastpage

127

Abstract

Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of α-criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%

Keywords

cellular arrays; circuit layout CAD; delays; genetic algorithms; integrated circuit layout; logic CAD; timing; α-criticality; IC design; area; connection length; critical paths; delay performance improvement; genetic algorithm; propagation delays; standard-cell placement; timing performance; timing-driven placer; wire length; Capacitance; Circuit testing; DH-HEMTs; Delay estimation; Genetic algorithms; Integrated circuit interconnections; Minerals; Propagation delay; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516037

Filename

516037