Title :
Test generation games from formal specifications
Author :
Banerjee, Ansuman ; Pal, Bhaskar ; Das, Sayantan ; Kumar, Abhijeet ; Dasgupta, Pallab
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur
Abstract :
In this paper, we present methods for automatic test generation from formal specifications. These are used to create intelligent test benches that are able to cover corner case behaviors in much less time. We have developed a prototype tool for intelligent test generation within the layered test bench architecture proposed in RVM. We present results on verification IPs of standard bus protocols to show the effectiveness of our approach
Keywords :
automatic test pattern generation; formal specification; RVM; automatic test generation; formal specifications; intelligent test generation; standard bus protocols; verification IP; Automatic testing; Chip scale packaging; Computer science; Electronic design automation and methodology; Formal languages; Formal specifications; Hardware design languages; Model driven engineering; Open systems; Prototypes; Realizability; Test Generation; Vacuity; Verification;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229273
