Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs

Author

Yoo, Jae-tack ; Brunvand, Erik ; Smith, Kent F.

Author_Institution

Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

fYear

1995

fDate

16-18 Mar 1995

Firstpage

148

Lastpage

151

Abstract

We describe a technique for translating semicustom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based environment. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and translated into Actel FPGAs. All test chips were found to be fully functional, and the translation efficiency in terms of chip speed and area is shown

Keywords

CMOS logic circuits; VLSI; circuit CAD; field programmable gate arrays; integrated circuit design; logic CAD; Actel FPGAs; CMOS IC; array multiplier; asynchronous pipelined version; automatic rapid prototyping; cell-matrix based environment; field programmable gate arrays; semicustom VLSI circuits; synchronous pipelined version; Automatic testing; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Field programmable gate arrays; Logic programming; Prototypes; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516042

Filename

516042