Characterization of electric charge in non irradiated and irradiated MOS structures by thermal step and capacitance-voltage measurements

The capacitance-voltage measurement (C-V), performed at frequencies higher than 10 kHz, has been so far the most used technique for measuring the charges present in Metal-Oxide-Semiconductor (MOS) structures. The C-V measurement allows to estimate the total amount of charge trapped within the SiO₂ layer which constitutes the insulator of the structure, but do not provide information about the charge distribution. The question if all the carriers trapped in the MOS structure are detected by C-V can also be asked. The aim of this work is to study the use of a method for space charge localization in insulating materials, namely the thermal step method (TSM), for characterizing MOS structures. The TSM has been adapted and applied to the short-circuited and biased MOS devices. A non irradiated and an irradiated MOS capacitor comprising a 100 nm thick SiO₂ layer are studied. The three operating modes of such devices under positive and negative bias (accumulation, depletion and inversion) are put into evidence, and the threshold voltage, which is affected by the space charge trapped in the oxide, is measured precisely. The results obtained by TSM, corresponding to measurement frequencies lower than 1 Hz, appear to be highly correlated with the C-V measurements, and seem to present a significant sensitivity. Estimations, by TSM, of the amount of charge trapped in the oxide and of the space charge penetration depth in the Si layer are presented.