DocumentCode
2472505
Title
Fast falsification based on symbolic bounded property checking
Author
Peranandam, Prakash M. ; Nalla, Pradeep K. ; Ruf, Jurgen ; Weiss, Roland J. ; Kropf, Thomas ; Rosenstiel, Wolfgang
Author_Institution
Tubingen Univ.
fYear
0
fDate
0-0 0
Firstpage
1077
Lastpage
1082
Abstract
Symbolic property verification is an increasingly popular debugging method based on binary decision diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper, we present accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation
Keywords
binary decision diagrams; logic testing; state-space methods; binary decision diagrams; debugging method; fast falsification; state space search; symbolic bounded property checking; symbolic property verification; Acceleration; Algorithm design and analysis; Automatic control; Boolean functions; Data structures; Formal verification; Input variables; Partitioning algorithms; Proposals; State-space methods; Fast Falsification; Guiding; Property Checking; Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229400
Filename
1688960
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