Digital timing recovery for communication systems

The paper presents a novel digital timing recovery mechanism for communication systems. The proposed approach jitters the ADC clock based on phase information obtained directly or indirectly from the received signal. The paper studies the effect of jitter resolution and its distribution on the timing SNR. It is demonstrated through simulations that the best SNR is achieved when the jitters are equally spaced. The proposed timing recovery scheme can be implemented by means of a numerically controlled oscillator (NCO), a tapped delay line, or a combination of the two. Practical aspects of all these schemes are presented. The resulting mechanism is able to achieve voltage controlled crystal oscillator (VCXO)-like performance at a much lower implementation cost. Although the proposed methodology can be applied to most communication systems, we focus on its application to asymmetric digital subscriber line (ADSL) modems.