Low complexity FPGA-implementation of a reconfigurable SIC multiuser detector for wireless applications

In this paper, we propose the low-complexity FPGA implementation of a reconfigurable successive interference cancellation (SIC) detector for combating the effect of multiuser interference in wired/wireless systems. The complexity of various building blocks is reduced and then the whole structure is pipelined. Using the PXI-7842R platform from National Instruments, the SIC detector is implemented and tested using a host-target model. Preliminary results indicate that up to 6 users can be accommodated for a 3-stage SIC detector with latency of 3.533 ns; this is much less than the chip duration (260.4 ns) and allows the real-time implementation of SIC detector. These results can be easily extended to a higher number of users if more powerful FPGA´s are employed.