Using EDIF for software generation

With the advent of the FPGA and parallel microprocessors the need for practical codesign methods is becoming increasingly important. This paper proposes that codesign can be approached from existing hardware development tools. The paper also reports on the development of a software tool which uses EDIF to generate parallel, real-time C code. The view taken is that the problematic issues of codesign are the same as those for optimising general parallel processing systems and that scheduling theory is the foundation of both codesign and parallel design environments