Title :
Simulation of Quantum Dot Flash Gate Stack with Lower Tunneling Voltages
Author :
Dhavse, R. ; Muhammed, F. ; Sinha, C. ; Mishra, V. ; Patrikar, R.M.
Author_Institution :
Electron. Eng. Dept., SVNIT, Surat, India
Abstract :
Tunneling voltage of a nano-scale flash memory cell needs to be lowered considerably. This can be done only by employing very thin tunnel dielectrics. Quantum dot floating gate devices have shown a potential to do so in sub-65 nm regime. In this work, conventional and quantum dots´ FGMOS gate stacks for 65 nm and 45 nm technology nodes are simulated in Synopsys TCAD. The experiments are simulated for metal control gate structures with ultra-thin oxides with 3.3 nm and 2.5 nm thicknesses. Quantum dots arrangement is optimized to give similar results as that of a conventional structure. The devices exhibit significant memory windows with tunneling voltages as small as 12 V and 6 V, respectively, with quantum dot devices further requiring lesser tunneling times.
Keywords :
MOSFET; dielectric materials; flash memories; integrated memory circuits; quantum dots; technology CAD (electronics); tunnelling; FGMOS gate stack; Synopsys TCAD; floating gate MOSFET; memory window; metal control gate structure; metal-oxide semiconductor field effect transistor; nanoscale flash memory cell; quantum dot flash gate stack simulation; quantum dot floating gate device; quantum dots arrangement; size 45 nm; size 65 nm; technology computer aided design; tunnel dielectric; tunneling voltage; ultrathin oxide; Capacitors; Logic gates; Nonvolatile memory; Quantum dots; Silicon; Threshold voltage; Tunneling;
Conference_Titel :
Devices, Circuits and Communications (ICDCCom), 2014 International Conference on
Conference_Location :
Ranchi
DOI :
10.1109/ICDCCom.2014.7024743