A new envelope predistortion linearization architecture for handset power amplifiers

The paper proposes a new envelope predistortion linearization architecture that utilizes low power analog components to correct intermodulation distortion (IMD) in RF power amplifiers (PAs). Log amps and phase detectors are used at the input and output of the PA to estimate the instantaneous complex gain. The outputs of the log amps and phase detector are fed back to a voltage controlled variable attenuator (VVA) and phase shifter (VVP), respectively, to correct any errors in the gain due to AM-AM or AM-PM distortion. As opposed to traditional envelope feedback approaches, this architecture achieves greater bandwidth by only feeding the distortion components back. Moreover, the distortion components are not added to the input signal as feedback, but they are used to predistort the input signal in a multiplicative manner. This architecture also allows correction of envelope memory effects that may occur in the PA. A behavioral model for Class-AB PA has been developed. The architecture has been verified by means of computer simulation using behavioral models extracted from a VVA, a VVP, and a 0.5 W GaAs HFET PA. For a cdmaOne signal with a bandwidth of 1.2288 MHz, the simulation shows an ACPR peak improvement of more than 10 dB over an output power dynamic range of 6 dB.