Implementation of low Vgs (1.8V) 12V RF-LDMOS for high-frequency DC-DC converter applications

A 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 μm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate formation with 30 Å gate oxide. Cut-off frequency 37.2GHz and 12.9GHz each for NLDMOS and PLDMOS were achieved with breakdown voltage of 20V. The long-term wafer level HCI test result showed Idlin shift under 10% after 150Ksec stress at Vds=12V and Vgs=1.8V.