Title :
Statistical estimation of delay fault detectabilities and fault grading
Author :
Zhang, Zaifu ; McLeod, Robert D. ; Bridges, Greg E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
Abstract :
In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detectabilities of delay faults. When compared with transition delay fault simulations, the estimations of fault coverage are within 2.3% for the benchmark circuits. Finally, the estimation technique is used to grade delay faults, with comparison to fault simulation results used to validate the method
Keywords :
VLSI; fault diagnosis; logic testing; statistical analysis; STAFAN; benchmark circuits; delay fault detectabilities; fanout free region; fanout stems; fault coverage; fault grading; gate line transition controllabilities; logic testing; statistical estimation; transition observabilities; Circuit faults; Circuit simulation; Circuit testing; Delay estimation; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Pattern analysis; System testing;
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
Print_ISBN :
0-8186-7035-5
DOI :
10.1109/GLSV.1995.516049