Title :
Intralevel mix and match lithography for sub-100 nm CMOS devices using the JBX-9300FS point-electron-beam system
Author :
Narihiro, M. ; Wakabayashi, H. ; Ueki, M. ; Arai, K. ; Ogura, T. ; Ochiai, Y. ; Mogami, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan
Abstract :
Electron Beam (EB)/Deep UV (DUV) intra-level mix and match (IL M&M) is one of the most attractive lithographic techniques, because it can achieve patterns which are smaller than the limit of optical resolution, and higher throughput than EB direct-writing. We have successfully fabricated sub-50 nm patterns on an 8-inch Si wafer by EB/DUV IL M&M with the JBX-9300FS advanced point-electron-beam system (acceleration voltage: 50 kV/100 kV, maximum beam-scanning rate: 25MHz, field size: 1mmx1mm at 50 kV/0.5 mm/spl times/0.5 mm at 100 kV, wafer size: 6/8/12 inch, and an in-line developer is included) and a conventional KrF stepper. We have developed a new method of preparing patterns to ensure that the EB patterns a reconnected with the KrF patterns. Our method has the advantage of making the arbitrary sized overlaps without depending on the minimum EB pattern size, compared to the method by Magoshi et al. We use a length criterion L/sub in/ to separate the original set of patterns into EB patterns and KrF patterns. Over laps a regenerated by a Boolean "AND" operation on the shifted EB patterns and the KrF patterns.
Keywords :
CMOS integrated circuits; electron beam lithography; nanotechnology; ultraviolet lithography; 100 nm; JBX-9300FS point-electron-beam system; deep UV lithography; intralevel mix and match lithography; sub-100 nm CMOS devices; Acceleration; Laboratories; Lithography; National electric code; Optical devices; Particle beams; Pattern matching; Resists; Throughput; Voltage;
Conference_Titel :
Microprocesses and Nanotechnology Conference, 2000 International
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-004-6
DOI :
10.1109/IMNC.2000.872678