DocumentCode
2473743
Title
Chip-package codesign with redistribution layer
Author
Suryakumar, Mahadevan ; Mekonnen, Yidnek ; Sarangi, Ananda
Author_Institution
Intel Corp., Chandler, AZ, USA
fYear
2009
fDate
19-21 Oct. 2009
Firstpage
231
Lastpage
234
Abstract
The use of redistribution layers to connect I/O circuit to the I/O pad is introduced and the electrical performance of a conceptual design with and without signal redistribution was compared.
Keywords
chip scale packaging; integrated circuit interconnections; I-O circuit; I-O pad; chip-package codesign; electrical performance; interconnect; redistribution layers; Copper; Impedance; Integrated circuit interconnections; Logic; Packaging; Propagation constant; Routing; Signal design; Silicon; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location
Portland, OR
Print_ISBN
978-1-4244-4447-2
Electronic_ISBN
978-1-4244-5646-8
Type
conf
DOI
10.1109/EPEPS.2009.5338434
Filename
5338434
Link To Document