Bit-pattern sensitivity analysis and optimal on-die-termination for high-speed memory bus design

System IO power and performance are critical computer platform design parameters. IO power forms a significant portion of the overall power while its performance is often the bottleneck in achieving overall performance specification. This paper experimentally demonstrates, for the first time, optimal on-die-termination (ODT) schemes for DDR3-800 MT/s and DDR31067 MT/s, revealed by thorough bit-pattern sensitivity analysis. Optimal ODT at IO receiver pads is proposed as a new critical design knob to achieve optimized power-performance trade-offs, dramatically improving signal integrity and power consumption. The thorough bit-pattern sensitivity analysis was found to be 100% more accurate than traditional approach. Up to 50% reduction in power consumption, 100% increase in timing margin, and 100% increase in voltage margin were demonstrated as the impact of the choice of ODT. It is also promised to become more important in the future at higher data rate.