DocumentCode
2474163
Title
Improved FPGA implementation of Probabilistic Neural Network for neural decoding
Author
Zhu, Xiaoping ; Chen, Yaowu
Author_Institution
Inst. of Adv. Digital Technol. & Instrum., Zhejiang Univ., Hangzhou, China
fYear
2010
fDate
17-19 Dec. 2010
Firstpage
198
Lastpage
202
Abstract
Probabilistic Neural Network has been considered as providing superior performance for neural decoding. However, the huge computation burden costs high resource in FPGA, which limits its scalability. In this paper, an improved FPGA implementation of Probabilistic Neural Network for neural decoding is developed and evaluated on the Xilinx Virtex-5 platform. The proposed implementation reduces the resource utilization, and enhances the scalability of the FPGA implementation of the Probabilistic Neural Network greatly.
Keywords
field programmable gate arrays; neural nets; FPGA; Xilinx Virtex-5 platform; neural decoding; probabilistic neural network; Artificial neural networks; Biological neural networks; Field programmable gate arrays; Probabilistic logic; Resource management; Table lookup; Training; CORDIC; FPGA; Mixed data size; Probabilistic Neural Network;
fLanguage
English
Publisher
ieee
Conference_Titel
Apperceiving Computing and Intelligence Analysis (ICACIA), 2010 International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-8025-8
Type
conf
DOI
10.1109/ICACIA.2010.5709882
Filename
5709882
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