A multi-region trap characterization method and its reliability application on STI-based high-voltage LDMOSFETs

Author

He, Yandong ; Zhang, Ganggang ; Zhang, Xing

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2012

fDate

3-7 June 2012

Firstpage

307

Lastpage

310

Abstract

The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Keywords

CMOS integrated circuits; MOSFET; electric breakdown; electron traps; interface states; semiconductor device reliability; LDMOS devices; MR-DCIV technique; OFF-state stress; STI drift regions; STI-based LDMOS transistor degradation; STI-based high-voltage LDMOSFET reliability; breakdown voltage; device electrical characteristics; direct current current-voltage technique; interface state generation; interface trap; laterally diffused metal-oxide-semiconductor devices; multiregion trap characterization method; on-resistance degradation; standard complementary metal-oxide-semiconductor process; two-dimensional device simulation; Degradation; Interface states; Logic gates; Stress; Substrates; Voltage measurement; High voltage LDMOS; degradation; interface state; multi-region direct current IV technique;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on

Conference_Location

Bruges

ISSN

1943-653X

Print_ISBN

978-1-4577-1594-5

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2012.6229084

Filename

6229084