Design and implementation of a lattice decoder for MIMO systems

Author

Ma, Jing ; Huang, Xinming

Author_Institution

Dept. of Electr. Eng., New Orleans Univ., LA, USA

fYear

2004

fDate

19-22 Sept. 2004

Firstpage

383

Lastpage

386

Abstract

This work presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder used in MIMO systems. The decoder algorithm has high data dependency during the closest lattice point search iteration. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The prototype of the decoder for a four-antenna system shows that it supports 2.7 Mbit/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.

Keywords

MIMO systems; digital signal processing chips; error statistics; field programmable gate arrays; iterative decoding; lattice theory; mobile handsets; parallel algorithms; search problems; 2.7 Mbit/s; BER performance; DSP; FPGA; MIMO systems; Schnorr-Euchner strategy; bit error rate; closest lattice point search iteration; data dependency; data preprocessing; four-antenna system; hardware architectures; lattice decoder; parallel algorithm; Bit error rate; Data preprocessing; Digital signal processing; Field programmable gate arrays; Hardware; Iterative decoding; Lattices; MIMO; Prototypes; Software prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Conference, 2004 IEEE

Print_ISBN

0-7803-8451-2

Type

conf

DOI

10.1109/RAWCON.2004.1389156

Filename

1389156