Design and implementation of a lattice decoder for MIMO systems

This work presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder used in MIMO systems. The decoder algorithm has high data dependency during the closest lattice point search iteration. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The prototype of the decoder for a four-antenna system shows that it supports 2.7 Mbit/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.