DocumentCode
2474516
Title
Power integrity optimization of 3D chips stacked through TSVs
Author
Ahmad, Waqar ; Zheng, Li-Rong ; Weerasekera, Roshan ; Chen, Qiang ; Weldezion, Awet Yemane ; Tenhunen, Hannu
Author_Institution
Sch. of Inf. & Commun. Technol., Dept. of Electron., Comput. & Software Syst., KTH, Kista, Sweden
fYear
2009
fDate
19-21 Oct. 2009
Firstpage
105
Lastpage
108
Abstract
On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.
Keywords
capacitors; distribution networks; integrated circuit modelling; optimisation; 3D chips; 3D integrated circuits; TSV pattern; decoupling capacitor; on chip power distribution network model; power integrity optimization; simultaneous switching; through silicon via; Circuit noise; Integrated circuit interconnections; Logic; Mathematical model; Network-on-a-chip; Power distribution; Power supplies; Power systems; Through-silicon vias; Voltage; Peripheral TSVs; Power distribution network; Power integrity;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location
Portland, OR
Print_ISBN
978-1-4244-4447-2
Electronic_ISBN
978-1-4244-5646-8
Type
conf
DOI
10.1109/EPEPS.2009.5338467
Filename
5338467
Link To Document